As one of the scaling technologies to increase the density of semiconductor devices, multi-gate transistors have been suggested, in which silicon bodies in a fin or nanowire shape are formed on a substrate, with gates then being formed on surfaces of the silicon bodies.
Multi-gate transistors that include a three-dimensional channel may allow for improved scaling. Further, current control capability can be enhanced without requiring increased gate length of the multi-gate transistor. Furthermore, it may be possible to effectively reduce or suppress short channel effect (SCE) which is the phenomenon that the electric potential of the channel region is influenced by the drain voltage.